1. Field of the Invention
The present invention relates to a multi-layer wiring board used for an electronic circuit board on which a semiconductor device housing package for housing therein a semiconductor device, a semiconductor device, an electronic component, or the like are mounted, and more particularly to a multi-layer wiring board having a wiring structure suitable for housing or mounting a semiconductor device which is operated at high speed.
2. Description of the Related Art
A multi-layer wiring board, on which electronic components including a semiconductor device such as a microprocessor, an ASIC (Application Specific Integrated Circuit), or a semiconductor integrated circuit device are mounted, is commonly used for an electronic circuit board or the like. Hitherto, in constituting a wiring conductor for usage in internal wiring, a multi-layer wiring board is formed by alternately stacking one on top of another insulating layers made of ceramics such as alumina, and wiring conductors made of metal having a high melting point such as tungsten (W).
In keeping with an increasing demand for improvements in data processing capability, a semiconductor device has come to be operated at higher and higher speed. As a result, out of wiring conductors for internal wiring, a signal wiring line is required to offer improved electric properties in terms of characteristic impedance matching, reduction in cross-talk noise between signal wiring lines, or other. In a conventional multi-layer wiring board, out of wiring conductors for internal wiring, a signal wiring commonly takes on a strip wiring structure. That is, a wiring conductor formed as a signal wiring line has, in its upper and lower parts, a wider-area ground layer or power source layer of so-called solid-pattern configuration formed via an insulating layer.
However, such a multi-layer wiring board as stated above has the following disadvantage. Since the insulating layer is made of alumina ceramics or the like having a relative dielectric constant of ca. 10, an electromagnetic coupling between the signal wiring lines becomes unduly great, resulting in an undesirable increase in cross-talk noise. This makes it impossible to handle increasingly higher operational speed of a semiconductor device.
In order to deal with higher-speed electric signals, attempts have been made to obtain a high-density, high-performance multi-layer wiring board capable of operating a semiconductor device at higher speed. For example, such a multi-layer wiring board is constructed as follows. An insulating layer is formed by using polyimide resin or epoxy resin having a relatively low relative dielectric constant in a range from 3.5 to 5, instead of alumina ceramics having a relative dielectric constant of ca. 10. On this insulating layer is formed an internal wiring conductor layer made of copper (Cu) by a thin-film forming technique based on a vapor-deposition method, such as an evaporation method or a sputtering method. Then, by using photolithography, a wiring conductor of fine pattern is formed, and the insulating layer and the wiring conductor are stacked in layers.
In order to reduce ringing noise by achieving wiring impedance matching, to reduce cross talk between signal wiring lines, and to realize high-density wiring, as an internal wiring structure designed for a multi-layer wiring board, such a structure is proposed that groups of parallel wiring lines are formed on the top surface of each insulating layer and they are stacked in layers, and, out of the wiring lines included in the layered wiring groups, specified ones are electrically connected to each other via a through conductor such as a via conductor or a through hole conductor.
In a multi-layer wiring board having such a parallel wiring group, to provide electrical connection between an electronic component, such as a semiconductor device, to be mounted on the multi-layer wiring board and amounting board for mounting thereon the multi-layer wiring board, with in the multi-layer wiring board, out of the wiring lines included in the groups of parallel wiring lines, suitable ones are selected. The selected wiring lines lying in different wiring layers are connected to each other via a through conductor such as a via conductor.
According to the multi-layer wiring board described above, as compared with the case where the signal wiring takes on a strip line structure, the number of the wiring layers can be reduced. Besides, inside the groups of parallel wiring lines, as well as in a region between the groups of parallel wiring lines, cross talk between the signal wiring lines can be reduced.
Moreover, one problem involved in power source supply for a semiconductor device is occurrence of simultaneous switching noise. Specifically, since a power-source voltage required for switching of the semiconductor device is supplied from the outside of the multi-layer wiring board through the power source wiring and ground wiring, when a plurality of signal wiring lines are concurrently subjected to the switching operation of the semiconductor device, noise is produced between the power source wiring and the ground wiring due to the inductance components included in the power source wiring or the ground wiring.
To overcome the above-stated problems, there has been adopted a method of incorporating within the multi-layer wiring board a capacitor composed of a wider-area power source wiring layer and a ground wiring layer, which are arranged so as to oppose each other via an insulating layer provided therebetween. By arranging the wider-area power source wiring layer and/or ground wiring layer in that way, it is possible to incorporate within the multi-layer wiring board a capacitor having a capacitance value as great as several nF. Consequently, the impedance value for the built-in capacitor is reduced, whereby making it possible to reduce the simultaneous switching noise. Note that the impedance value is proportional to the square root of the inductance value but is inversely proportional to the square root of the capacitance value. It has been known that, in general, the smaller the impedance value for the built-in capacitor, the less the simultaneous switching noise. Further, to obtain as large a capacitance value as possible, an attempt has been made to form a plurality of capacitors within the multi-layer wiring board.
However, the above-described multi-layer wiring board, provided with the groups of parallel wiring lines arranged orthogonally with respect to each other, also encounters a problem of EMI (Electro Magnetic Interference) noise, as the result that an electronic component, such as a semiconductor device, to be mounted thereon has come to be operated at higher and higher speed. The EMI noise mentioned just above may be explained as follows. If electronic equipment of various types emit an unnecessary electromagnetic wave, the electromagnetic wave finds its way into the electronic equipment or other peripheral electronic equipment, so that it becomes noise and exerts an adverse effect on the electric circuits. This brings the electronic equipment into malfunction.
Besides, as further improvement has been eagerly sought in data processing capability, the operational speed of a semiconductor device has been rapidly increased and, for example, a semiconductor device has come to be operated at a frequency of greater than 1 GHz. As a natural consequence of this trend, another problem arises that unduly large simultaneous switching noise is caused by a harmonic component included in an electric signal which is transmitted to the interior of the multi-layer wiring board.
The harmonic component refers to a frequency component having a relatively high frequency included in a digital signal. The harmonic component is increased in component proportion at a frequency which is equivalent to an integral multiple of the operating frequency (fundamental wave) of the semiconductor device, but is decreased in component proportion as its frequency becomes higher and higher. It has been known that in particular a harmonic component having a frequency up to ca. 5 times higher than the operating frequency is largish in component proportion. In light of this fact, the impedance value needs to be reduced also at a band of frequencies which are ca. 5 times higher than the operating frequency.
Hereupon, in the above-described conventional multi-layer wiring board incorporating a capacitor composed of a wider-area power source wiring layer and/or ground wiring layer that are arranged so as to oppose each other via an insulating layer disposed therebetween, because of its structure in which the built-in capacitor having a specific capacitance value is formed, the impedance value can be reduced at the frequency band close to the operating frequency by setting the resonance frequency, included in the impedance characteristics of the built-in capacitor, to be close to the operating frequency of the semiconductor device. However, in this construction, no consideration is given to the impedance value at the frequency band of the harmonic component. Therefore, in the region in which the operating frequency of the semiconductor device is low, the simultaneous switching noise can be reduced successfully, whereas in the high-frequency region in which the operating frequency exceeds several GHz, the impedance value for the built-in capacitor becomes unduly large and accordingly the simultaneous switching noise is increased.
Moreover, in a case where the anti-resonance frequency included in the impedance characteristics of the built-in capacitor coincides with the frequency of the harmonic component, the harmonic component acts as electromagnetic noise on the power source wiring and the ground wiring, resulting in an undesirable increase in the EMI noise.
The invention has been devised to solve the above-described problems, and accordingly its object is to provide a multi-layer wiring board suitable for an electronic circuit board on which an electronic component operating at high speed such as a semiconductor device is mounted, which is characterized in that: groups of parallel wiring lines are orthogonally stacked on top of each other; cross-talk noise occurring between adjacent wiring lines can be reduced without sacrificing the electric properties; and simultaneous switching noise, as well as EMI noise, can be reduced successfully.
The invention provides a multi-layer wiring board comprising:
an insulating substrate including a first insulating layer and a second insulating layer stacked on the first insulating layer, the insulating substrate having, on a central part of a top surface thereof, a semiconductor device mounting portion with a semiconductor device connecting electrode attached thereto, and having, on an under surface thereof, an external electrode for supplying electric power to the semiconductor device;
a multilayered wiring including a first group of parallel wiring lines formed on the first insulating layer, the parallel wiring lines, in each of divided sections that are obtained by dividing the multi-layer wiring board into several sections by two to four straight lines intersecting at a center of the first insulating layer in such a way that central angles of the divided sections are made substantially equal to each other, being so formed as to extend toward the intersection, a second group of parallel wiring lines formed on the second insulating layer, the parallel wiring lines, in each of the divided sections, being respectively arranged orthogonally with respect to the parallel wiring lines constituting the first group of parallel wiring lines, and a group of through conductors for providing electrical connection between the first and second groups of parallel wiring lines, and built-in capacitors provided in an interior of the insulating substrate, the built-in capacitors having a power source wiring layer and a ground wiring layer which are arranged to oppose each other via an insulating layer disposed therebetween,
wherein electric power is supplied from the external electrode to the semiconductor device through the built-in capacitors,
and wherein the built-in capacitors have mutually different resonance frequencies within a range from an operating frequency band for the semiconductor device to a frequency band for a harmonic component, are connected in parallel with each other, and at an anti-resonance frequency occurring between the different resonance frequencies, a composite impedance is set to be equal to or less than a predetermined value.
According to the invention, the multi-layer wiring structure, in which the groups of parallel wiring lines are orthogonally stacked on top of each other, includes a multilayered wiring constructed as follows. The structure is divided into several sections by two to four straight line intersecting at the center of the first insulating layer, with the central angles of the sections made substantially equal to each other. In each of the divided sections, the first and second groups of parallel wiring lines are provided. The first group of parallel wiring lines is composed of a plurality of parallel wiring lines that are disposed so as to extend substantially parallelly in a direction toward the intersection, i.e. the central part of the first insulating layer, and the second group of parallel wiring lines is composed of a plurality of parallel wiring lines that are disposed so as to extend substantially parallelly in a direction orthogonal to the group of parallel wiring lines of the first wiring layer. The first and second groups of parallel wiring lines are electrically connected to each other by the through conductor group. In this structure, the wiring lines constituting the second group of parallel wiring lines are arranged substantially circumferentially about the center of the second insulating layer. This substantially circular wiring structure yields the effect of preventing external intrusion of EMI noise and the effect of shielding against external radiation of unnecessary electromagnetic noise. Hence, the multi-layer wiring board embodying the invention succeeds in minimizing the cross-talk noise occurring between the wiring lines without sacrificing the electric properties of the groups of parallel wiring lines, and also succeeds in achieving effective EMI control.
Moreover, the divided sections are defined by two to four straight lines intersecting at the center of the first insulating layer, with their central angles made substantially equal to each other. Consequently, the wiring flexibility can be enhanced and thus the wiring length can be shortened, so that the resistance, inductance, and capacitance can be minimized.
According to the invention, inside the insulating substrate is provided built-in capacitors for supplying electric power which have a power source wiring layer and a ground wiring layer arranged to oppose each other via an insulating layer disposed therebetween. The built-in capacitors are connected in parallel with each other that have different resonance frequencies within a range from the operating frequency band for the semiconductor device to the frequency band for the harmonic component. In this structure, the resonance frequency, at which the impedance value is kept at a minimum, can be so set as to vary in the individual built-in capacitors within the range from the operating frequency band for the semiconductor device to the frequency band of the harmonic component. Further, the composite impedance at the anti-resonance frequency occurring between the different resonance frequencies is set to be equal to or less than a predetermined value. Consequently, in the range from the operating frequency band for the semiconductor device to the frequency band of the harmonic component, the composite impedance value can be minimized over a wider frequency band.
In the invention, it is preferable that the composite impedance value at the anti-resonance frequency is set to be 1 xcexa9 or below.
According to the invention, by setting the composite impedance value at the anti-resonance frequency to be 1 xcexa9 or below, the inductance components included in the power source wiring layer and the ground wiring layer can be minimized. Consequently, the simultaneous switching noise can be reduced at the high-frequency band where the semiconductor device is operated at a frequency greater than several GHz, as well as at the frequency band of the harmonic component.
Moreover, since the power source wiring layer and the ground wiring layer are made to have a wider area, it is possible to form a built-in capacitor having a capacitance value as large as several nF. Consequently, the simultaneous switching noise can be reduced also at the low-frequency band where the semiconductor device is operated at a frequency as low as several MHz.
Further, the anti-resonance frequency, included in the impedance characteristics of the built-in capacitor, can be set at a value incoincident with the frequency of the harmonic component included in an electric signal, by controlling the capacitance values for the built-in capacitors. This makes it possible to reduce the EMI noise.
In the invention, it is preferable that the first and second groups of parallel wiring lines each include a plurality of signal wiring lines and power source wiring lines or ground wiring lines arranged adjacent to the signal wiring lines.
According to the invention, the first and second groups of parallel wiring lines each include a plurality of signal wiring lines and power source wiring lines or ground wiring lines arranged adjacent to the signal wiring lines. In this structure, the signal wiring lines disposed on the same insulating layer are electromagnetically cut off from each other, and thereby the cross-talk noise occurring between the signal wiring lines arranged side by side on the same plane can be reduced successfully. Further, by arranging the power source wiring line or the ground wiring line adjacent to the signal wiring line without fail, the interaction between the signal wiring line and the power source wiring line or the ground wiring line, arranged on the same plane, can be maximized, thereby decreasing the inductance of the power source wiring line and the ground wiring line. Reduction in the inductance makes possible effective reduction in power source noise and ground noise.
In the invention, it is preferable that the second group of parallel wiring lines includes a circular wiring which is constituted by connecting the wiring lines lying in the individual divided sections.
According to the invention, the second group of parallel wiring lines includes a circular wiring constituted by connecting the wiring lines lying in the individual divided sections. By providing such a circular wiring, it is possible to cope with EMI noise effectively, thereby achieving more effective EMI control.
In the invention, it is preferable that an outermost circular wiring of the second group of parallel wiring lines is a ground wiring.
According to the invention, the second group of parallel wiring lines has its outermost circular wiring made as a ground wiring. This circular ground wiring brings about remarkable EMI-noise shielding effect, whereby making it possible to achieve far more effective EMI control.
In the invention, it is preferable that the built-in capacitors are made different from each other in resonance frequency by varying the sizes of the oppositely-arranged power source wiring layers and ground wiring layers of the built-in capacitors.
In the invention, it is preferable that the built-in capacitors are made different from each other in resonance frequency by varying dielectric constants of the insulating layers lying between the oppositely-arranged power source wiring layers and ground wiring layers.
In the invention, it is preferable that the built-in capacitors are so designed that the anti-resonance frequency associated with impedance characteristics is set at a value incoincident with the operating frequency of the semiconductor device.
In the invention, it is preferable that, out of the built-in capacitors, the one arranged closer to the semiconductor device mounting portion is made higher in resonance frequency.
In the invention, it is preferable that the power source wiring layers and the ground wiring layers, constituting the built-in capacitors, are formed on layers other than that on which the first and second groups of parallel wiring lines are formed.
According to the invention, there is realized a multi-layer wiring board suitable for an electronic circuit board or the like on which an electronic component operating at higher speed, such as a semiconductor device, is mounted. The multi-layer wiring board is provided with groups of parallel wiring lines which are orthogonally stacked on top of each other, and thus succeeds in minimizing cross-talk noise occurring between adjacent wiring lines without sacrificing the electric properties, and also succeeds in minimizing simultaneous switching noise as well as EMI noise.
The invention further provides a multi-layer wiring board comprising:
an insulating substrate constituted by stacking a plurality of insulating layers on top of each other, the insulating substrate having, on a top surface thereof, a semiconductor device connecting electrode, and having, on an under surface thereof, an external electrode for supplying electric power to the semiconductor device; and
built-in capacitors provided in an interior of the insulating substrate, the built-in capacitors having a power source wiring layer and a ground wiring layer which are arranged to oppose each other via the insulating layer disposed therebetween,
wherein electric power is supplied from the external electrode to the semiconductor device through the built-in capacitors,
and wherein the built-in capacitors have mutually different resonance frequencies within a range from an operating frequency band for the semiconductor device to a frequency band for a harmonic component, are connected in parallel with each other, and at an anti-resonance frequency occurring between the different resonance frequencies, a composite impedance is set to be equal to or less than a predetermined value.
According to the invention, inside the insulating substrate is provided built-in capacitors for supplying electric power having a power source wiring layer and a ground wiring layer arranged to oppose each other via an insulating layer disposed therebetween. The built-in capacitors are connected in parallel with each other that have different resonance frequencies within a range from the operating frequency band for the semiconductor device to the frequency band for the harmonic component. In this structure, the resonance frequency, at which the impedance value is kept at a minimum, can be so set as to vary in the individual built-in capacitors within the range from the operating frequency band for the semiconductor device to the frequency band of the harmonic component. Further, the composite impedance at the anti-resonance frequency occurring between the different resonance frequencies is set to be equal to or less than a predetermined value. Consequently, in the range from the operating frequency band for the semiconductor device to the frequency band of the harmonic component, the composite impedance value can be minimized over a wider frequency band.
According to the invention, there is provided a multi-layer wiring board suitable for an electronic circuit board or the like on which an electronic component operating at higher speed such as a semiconductor device is mounted, in which simultaneous switching noise and EMI noise can be reduced successfully.